Performance Analysis of Vedic Multiplier and Modified Vedic Multiplier in Direct Digital Synthesizer

In most digital applications, the usage of multipliers impacts the speed of operation as well as utilizes maximum space. The evaluation of high-speed multipliers that adapt the reconfigurable structure of repeatable blocks is required to reduce the space. The proposed Vedic Multiplier Vedic Synthesizer (VMVS) system implements low latency techniques in Direct Digital Synthesizer (DDS) coupled to the output of the Vedic multiplier. The component is initiated once and called up at every iteration on demand. The DDS is the unique word-controlled Digital Phase-locked loop that enables stable clock output at every locking condition. The achievement of the proposed design is that latency is reduced by 14% and power by 0.001w. The crafted structure produces synthesizable VMVS to produce the adaptable output and stable clock.