A 0.0022 mm² 10 bit 20 MS/s SAR ADC With Passive Single-Ended-to-Differential-Converter

This paper proposes a passive switched-capacitor single-ended-to-differential-converter (SDC) as a front-end of a differential SAR ADC, such that it can convert single-ended input signals. As the SDC is passive, the overall solution is power-efficient compared to active SDC solutions, and is especially suitable for lower/medium resolutions. As opposed to active SDC solutions with a static bias current, the proposed switched-capacitor network only consumes dynamic power, such that its consumption scales linearly with the sampling frequency. This paper discusses the basic concept of the proposed scheme, and analyzes the impact of noise and other imperfections, describes the trade-offs for power and area, and discusses the consequences for the input driver. A prototype implementation in 65nm CMOS achieves a figure-of-merit of 6.1fJ/conversion-step at 20MS/s, while reaching an SNDR of 54.7dB up to Nyquist and occupying a chip area of only
$60~\mu \text{m}\,\,\times 36~\mu \text{m}$
.