Enabling 3-level High Aspect Ratio Supervias for 3nm nodes and below

High aspect-ratio (AR) 3-level Supervias (SV), with a minimum bottom CD of 15.5 nm and AR = 7.7 are successfully integrated in a 3nm node chip. 3-level SV directly connects M
x
with M
x+3
metal layers, without connecting to the intermediate two metal layers. Enabling such high AR SV is achieved by fine tuning the SV etch process to guarantee uniform SV landing and a straight vertical profile. Electrical results show that 3-level Kelvin SVs provide an average resistance of 58 Ω, yielding > 95 % for the best conditions, improving our previously reported yield values of 2-level with enhanced AR [1]. 3-level SVs gave a resistance 13% lower than the conventional 2-level stacked via configuration [2]. Metallization stack used was 0.3 nm of ALD TiOx as an adhesion layer, followed by a Ru CVD deposition of 70 nm. Thermal shock tests of 500 hours, between −50 °C and 125 °C, performed on intervals of 15 min each, showed that the Kelvin resistance values remained virtually unchanged. Therefore, 3-level SV are stable after thermal shock tests, proving that they are a robust scaling booster for the 3nm node.