A 1.5 V 2 GS/s 82.1 dB-SFDR Track and Hold Circuit Based on the Time-Divided Post-Distortion Cancelation Technique

This brief presents a track and hold (T/H) circuit for time-interleaved analog-to-digital converters based on a new linearization technique—time-divided post-distortion cancellation. Fabricated in 65 nm CMOS, it achieves 82.1 dB SFDR with a 700-mV near-Nyquist input at a clock speed of 2 GS/s, while drawing only 9 mW power from a 1.5-V supply. Compared to the previous state-of-the-art circuits, this T/H circuit exhibits an energy-efficiency figure-of-merit improvement of 9.5 dB.