The Design of a Fast Front-end Readout ASIC for Time Correction with Low Voltage

An ultra-fast leading edge readout ASIC designed for high resolution time correction of the timing Resistive-Plate Chambers (RPCs) is presented in this work. This front-end readout architecture is featured with the high bandwidth preamplifier and the following fast discriminator. The input impedance of preamplifier can be adjusted externally to match the detector, and the discrimination threshold can be changed independently in every readout channel. Implemented in 0.13μm CMOS process, the proposed ASIC can realize a time jitter of 10ps and its power dissipation is about 6.1 mW/channel, both are better than that of similar chips.