Fast Radix-2 Montgomery Modular Multiplication on FPGA Using Ternary Adder

The most time-consuming operation in Elliptic Curve Cryptography (ECC) is modular multiplication. A series of FPGA implementations of various modular multiplication algorithms have been developed thus far, aiming at reducing the computation time. In this paper, a radix-2 Montgomery multiplication architecture is presented, the main element of novelty being the use of a single ternary (i.e. three-input) adder instead of the pair of adders used in other architectures. The proposed design was implemented on a Xilinx Virtex-7 FPGA, obtaining maximum multiplication times of 0.62 µs, 0.79 µs, 0.94 µs, 1.51 µs and 2.18 µs for operands of 192, 224, 256, 384 and 521 bits, respectively. In a comparative analysis with other radix-2 architectures, the experimental results show that the proposed design brings a notable improvement in multiplication time, throughput and maximum operating frequency, while having a high area-time efficiency.