A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs

Continuous-time pipelined (CTP) ADCs have shown the potential to alleviate the challenges of discrete-time (DT) pipelined converters with Multi-GHz bandwidth, but have so far required an oversampling ratio (OSR) of at least 4. After elucidating the factors that limit CTP bandwidth, this paper presents a design methodology for near-Nyquist CTP ADCs. The delay circuit is optimized to match the ADC/DAC path in both its broadband magnitude response and phase. The residue filter response is optimized to prevent image signals from overloading the subsequent stage. We show that practical circuits can realize these optimized responses and extend the bandwidth of the CTP architecture to OSRs of 1.5-2.0, essentially equivalent to the OSR of DT converters when allowing for practical anti-aliasing. The direct path (i.e. delay) and the residue-amplifying filter circuits required for 3 GHz bandwidth are incorporated into a complete 4-bit 10 GS/s CTP ADC stage in a 28nm CMOS prototype. Simulation and measurement results confirm that CTP ADCs can operate at a near-Nyquist sampling rate with an OSR of 1.7.