FPGA-based HDLC Controller Design and Communication Implementation in Normal Response Mode

High-Level Data Link Control is a bit-oriented link-layer transmission protocol widely used in communication and measurement and control equipment with high reliability and transparent transmission. In order to solve the problems of low flexibility of ASIC chip and high CPU resource consumption of software implementation, this paper designs an HDLC controller with Verilog HDL in the Xilinx platform and completed the module simulation verification and hardware test of communication under the normal response mode; the results show that the controller has stable data transmission, low resource consumption, and robust error correction capability.