Failure analysis and improvement research on high lead solder bump of flip chip FPGA for aerospace

More aerospace electronic equipment use flip-chip packaged FPGA to implement system functions, so as to improve the functional processing performance of spacecraft. This also puts forward higher requirements for the reliability of interconnect materials in FPGA packages. Material selection and soldering interface structure have a significant impact on package reliability. In this paper, composition analysis and SEM in-situ characterization is conducted to analyze the failure reasons for bump solder interface cracking of one type of anti-radiation flip-chip FPGA for aerospace use. Results show that when the flip chip is soldered with 90Pb10Sn solder bumps to the ceramic substrate, the gold layer of substrate pad dissolved in liquid lead and forming Au-Sn compounds. Driven by the reduction of interfacial free energy, the as formed AuSn
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enriched at UBM solder interface and formed brittle intermetallic compound layer. Based on failure mechanism, the chip was packaged with 63Sn37Pb bumps instead of 90Pb10Sn solder. After changing solder material, there was no cracking or layered gold-tin compound at the soldering interface, and the device passed environmental assessment test.