Stress Analysis and Layout Optimization of Nano-TSV in an Advanced Packaging

The technique of the through silicon via (TSV) filling with copper plays an important role in the 3D packaging to miniaturize connection distance, decrease energy consumption and improve integration density. The nano-scale TSV of the vertical interconnection is obligatory to be developed to reach sub-micron interconnect pitches. However, the reliability of the nano-TSV is a serious concern because thermo-mechanical stresses are varied in the TSV under thermal loadings due to the mismatch of the coefficients of thermal expansion (CTE) between the copper and the surrounding silicon. The high stresses may cause crack propagation and even failures. In this study, the finite element analyses (FEA) for the nano-TSV array with different sizes and patterns were performed. The submodeling method was used in the analysis for a 3D packaged device to reveal the influence of the critical parameters, i.e., the aspect ratio of TSV, the ratio of pitch to diameter and the TSV array layouts. The trilateral and quadrilateral layouts of nano-TSV array were considered in the analysis. Thus, appropriate design suggestions for the nano-TSV array were proposed. The study results assist to optimize the nano-TSV geometry and improve the reliability of the 3D package with nano-TSV.