Characterizations of micro bump undercuts for chiplets integrated packaging

To satisfy the increasing demands for IC functionality, the advanced packaging is strongly pursued. As its important part to connect chips, micro bumps can achieve high I/O counts by decreasing interconnect pitch and increasing interconnect density. Due to the size reduction of micro bumps, its undercut effect becomes significant and results in missing bumps or prematurely failures. This paper presents two kind of micro bumps, including Ni/SnAg bumps and Cu/Ni/SnAg bumps. Then, we discuss the producing mechanism of their undercuts, and present their solutions. In the result, the galvanic effect would be a trigger for Ni/SnAg bumps to have a larger size of undercuts than that of Cu/Ni/SnAg bumps. By reducing the thickness of the seed layer Cu and the Ni of Ni/SnAg bumps, it could effectively decrease the undercut size. Adding a Polyimide (PI) layer would also protect Ni/SnAg bumps from the missing bump. However, those methods above were difficult to control the undercut size in target (less than 1μm at single side). Therefore, three alternative etchants for etching the seed layer Cu were evaluated, which aiming to reduce the undercut size further. Finally, the undercut sizes of Ni/SnAg bumps and Cu/Ni/SnAg bumps can be controlled at 0.5μm and 0.6μm, respectively.