Reliability study of 3D IC structure under thermal power consumption load by Finite Element Simulation

According to Moore's law, it becomes more and more difficult to improve the performance of integrated circuits by reducing the size of transistors. As research and application direction surpasses Moore's law, three-dimensional integrated circuit (3D IC) has been greatly developed. Due to the increasingly narrow spacing between stacking chips and the pitch of micro-bumps. It is time-consuming and labor-consuming to study its reliability only through traditional experimental methods. Therefore, it is particularly important to study its reliability when it is operating by numerical simulation. In this paper, a three-dimensional chip structure based on hybrid bonding and back-TSV (Through Silicon Via) was established. Based on the Annad viscoplastic constitutive equation for micro bumps, the stress situation of the three-dimensional chip under thermal consumption load was simulated by the finite element method, and the weak area of the packaging structure was revealed. Meanwhile, the deformation of the three-dimensional chip under the action of the heat source is obtained, especially the deformation of micro bumps. The temperature distribution of the whole model is also obtained after operating for about several hours, and the dissipation energy of a solder bump node was calculated. The results show that the working temperature of the structure can reach about 72, and the maximum value of the micro-bumps stress appears at the edge. At the same time, the bump will show an obvious plastic flow phenomenon under the action of thermal load.