Methods for Delayering Integrated Circuits using a Broad Ion Mill

Chip delayering is an important technique for hardware security analysis. It allows for reverse engineering of an integrated circuit’s structures, finding possible security flaws, and in some cases enabling secret key extraction. This paper presents methods to prepare single subsequent layers of an IC for imaging purposes using a Broad Ion Beam System (BIBS). These methods consist of parameter sets (angle, energy, duration) for the etching process steps which have to be applied in a specific order. These parameter sets were developed by first analysing separately the impact of the single parameters on the etch rate and the IC’s surface structures. Development then split into etchrate-matched and direct beam methods aiming both at planar delayering with little operator intervention. Both methods were put to the test on state-of-the-art microcontrollers with 250nm (Chip A) and 180nm (Chip B) feature size.