Warpage Simulation and Analysis for FOWLP with Metal Carrier

Fan-out technology expands the space of the package by embedding silicon dies in epoxy molding compound (EMC), thereby supporting more I/O counts. However, due to the functional group cross-linking reaction of EMC, viscoelastic relaxation, and coefficient of thermal expansion (CTE) mismatch between different materials, the warpage will increase during the process of reconstituted wafer, which will affect the reliability of electronic product. In addition, the package structure will also have a certain impact on the warpage value.This study focuses on the influence of key parameters such as package structure and carrier material properties on wafer warpage, we use finite element analysis (FEA) to simulate the warpage of the reconstituted wafer after removing the metal carrier. The evolution of warpage with/without metal carrier during temperature altering are investigated in detail by FEA. The element birth and death technique in FEA is applied to simulate the effect of removing the metal carrier. The warping trend of linear elastic model and viscoelastic model of EMC is the same, but the final results differ greatly. By comparing the simulation results, we find that the fan-out ratio can be increased by decreasing the size of silicon chip or increasing the package size, thus reducing the warpage value. Similarly, thickness of die and EMC also have a certain influence on warpage. Increasing the thickness and Young's modulus of the carrier, or decreasing its CTE, can obviously reduce the warpage in the process, but the warpage value is basically the same after the carrier is removed. We believe that our study has certain guiding significance for warpage controlling of FOWLP by structural design or carrier material selection.