Electron and hole mobility in silicon at large operating temperatures. I. Bulk mobility

In this paper, an experimental investigation on high-temperature carrier mobility in bulk silicon is carried out with the aim of improving our qualitative and quantitative understanding of carrier transport under ESD events. Circular van der Pauw patterns, suitable for resistivity and Hall measurements, were designed and manufactured using both the n and p layers made available by the BCD-3 smart-power technology. The previous measurements were carried out using a special measurement setup that allows operating temperatures in excess of 400/spl deg/C to be reached within the polar expansions of a commercial magnet. A novel extraction methodology that allows for the determination of the Hall factor and drift mobility against impurity concentration and lattice temperature has been developed. Also, a compact mobility model suitable for implementation in device simulators is worked out and implemented in the DESSIS/spl copy/ code. Comparisons with the mobility models by G. Masetti et al. (1983) and D.B.M. Klaassen (1992) are shown in the temperature range between 25 and 400/spl deg/C.