Application of logical effort on design of arithmetic blocks

In this paper, we review the logical effort model presented in Sutherland et al. (1991). Based on the HSPICE simulation results using 0.18 /spl mu/m CMOS technology as applied to logic blocks used in arithmetic circuits; we analyze the efficiency of the model and also present modifications that include modeling of wire delay. We propose a new model for logical effort that better fits the behavior of these blocks. The results are applicable for evaluation of arithmetic units as well as for development of new arithmetic algorithms. Our ultimate objective is to close the gap between arithmetic algorithms and their performance in VLSI CMOS.