A Process and Data Variations Tolerant Capacitive Coupled 10T1C SRAM for In-Memory Compute (IMC) in Deep Neural Network Accelerators

Advanced processors suffer from Von-Neumann bottleneck and In-Memory Compute (IMC) based solutions are proposed to improve performance and reduce power consumption by bypassing this bottleneck. In this work, we present a 10T1C SRAM cell that enables process and data variation tolerant robust compute operation. The cell is 33% more linear than competing architectures and also enables much higher parallelism (higher throughput) due to 40X lesser variability. A sample IMC SRAM instance in 65nm Low Standby Power Technology with 4-bit flash ADC and digital adder operates at an energy efficiency of 350 TOPS/W.