TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network

In this paper, an energy-efficient computing-in-memory architecture using 10T-SRAM cells is proposed to resolve the design challenges of mixed-signal Computing-in-memory (CIM) schemes. A time-assisted current-based (TAC-based) MAC and ADC mechanism is developed to maintain good linearity throughout the multiplication and AD conversion process. A binary-search discharge-based ADC (DB-ADC) ensures high energy efficiency and throughput in high precision mixed-signal computations. A 4Kb SRAM array is fabricated in TSMC 65nm CMOS process and measurement results show that a throughput of 24.1 GOPS and a peak energy efficiency of 57.55 TOPS/W are achieved with multi-bit MAC operation for 4-bit input, 1-bit binarized weight, and 11-bit signed output.