Gate Voltages Impacting on Latch-up Measurements

Integrated Circuits (ICs) are often turned off under latch-up measurements. One power IC is often applied with a large size for driving capabilities. The large size device is often difficult to be turned off under latch-up stresses. In this paper, device behaviors of different gate biased voltages applied on large size devices under latch-up measurements are discussed. From the silicon data analyses, latch-up current paths changed from MOSFET to the parasitic diodes are observed well so the false latch-up test is verified. Finally, over voltage test is proposed for turned-on large size devices' latch-up measurements.