The impact of electrothermal stress on threshold voltage drift of gan and SIC cascode devices

Gallium Nitride (GaN) and Silicon Carbide (SiC) power cascode devices both take advantage of a low-voltage enhancementmode Silicon power MOSFET coupled with a high-voltage depletion-mode GaN HEMT or SiC JFET to realize high switching frequencies with the intention of avoiding charge trapping and threshold voltage drift in the gate oxide traps of enhancementmode SiC MOSFETs. Nevertheless, in this paper it is shown that SiC and GaN Cascodes will also suffer from the gate threshold voltage drift when subjected to significant electrothermal stress. This is partly due to the natural drift of threshold voltage in the gate, and partly due to the impact of the leakage current by the high-voltage device. The threshold voltage drift can lead to permanent degradations and potential failures, and as such is the subject of this investigation.