A 18–50 GHz Two-Phase Mixer-First Receiver Front-End in 45-nm SOI

An 18–50 GHz mixer-first receiver implemented in 45-nm SOI CMOS is presented. The receiver employs a differential quadrature coupler to split received signal into I/Q and provide broadband input match, a two-phase double balanced passive mixer to downconvert the signal, a low-power inverter based LO driver with series resonance peaking to flatten driver gain across frequency and a baseband LNA with 2
^nd
order Sallen-Key low pass filter. Authors believe this to be the first demonstration of 18–50 GHz reconfigurable, low power (< 50 mW) and linear (5 dBm IIP3) 2-phase mixer-first receiver chip.