Hybrid MoCs for Long-Distance On-Chip Communications

The contemporary networks-on-chip (NoCs) are becoming a viable on-chip communication architecture to serve the demand of high-performance requirements of multicore platforms. Mesh-based NoCs (MoCs) that provide efficient, interconnected infrastructures are popularly accepted as the scalable medium to the requirements. However, the MoCs fall short of meeting the stringent system requirements while the network size increases and resulting in the issue of long-distance communications. This paper presents altering a traditional MoC to corresponding Hybrid architecture that addresses the problem and provides improved performance. The proposed scheme transforms an MoC with a few wireless routers to handle the long-distance communication in MoCs. Evaluation of the proposed method on a 32-bit
$8\times 8$
Hybrid MoC shows that the network achieves latency as of 30167.897 cycles, network throughput of 12.8824 flits/cycle, and energy consumption as of
$29.9182\ \mu\mathbf{J}$
, respectively. Compared to the traditional
$8\times 8$
MoC, the proposed Hybrid architecture improves packet loss, latency, and throughput metrics up to 96%, 98.36%, and 25.77%, respectively. This achievement is about
$8\times$
faster than many existing approaches.