Bilateral 60-V Amorphous InGaZnO Thin-Film Transistors With Symmetric Stair Gate Dielectric

This work implemented bilateral 60-V amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) with symmetric stair gate dielectric at the contact sides. The stair gate dielectric lowers the electrical field between the gate and the contacts, enhancing the breakdown voltage (
${V}_{\text {BD}}$
). The
${V}_{\text {BD}}$
was improved from sub-20 to 60 V and a bilateral
${V}_{\text {BD}}$
of 60 V was achieved at the total stair length (
${L}_{\text {stair}}$
) of over
$2.9~\mu \text{m}$
for the proposed device. The transconductance (
${G}_{m}$
) degrades with the increasing
${L}_{\text {stair}}$
, attributed to the rising equivalent thickness of the stair gate dielectric. The gate-four-probe (GFP) method measurements reveal that the ON-resistance (
${R}_{ \mathrm{\scriptscriptstyle ON}}$
) of the stair gate region has a linear dependence on the
${L}_{\text {stair}}$
. The increasing electron concentration in the channel outside the stair region optimizes the output current, as confirmed by the TCAD simulation. The breakdown properties of the devices with a small
$L_{\text {stair}}$
(
$ < 0.1~\mu \text{m}$
) were also simulated. The proposed symmetric stair gate dielectric a-IGZO TFTs possessed low
${R}_{ \mathrm{\scriptscriptstyle ON}}$
and high
${V}_{\text {BD}}$
at the same time.