280.2/309.2 GHz, 18.2/9.3 dB Gain, 1.48/1.4 dB Gain-per-mW, 3-Stage Amplifiers in 65nm CMOS Adopting $\text{Double-embedded-}G_{max}\text{-core}$

This paper reports a sub-THz high-gain amplifier design technique which is more flexible and suitable for performance optimization based on a
$\text{double}\text{-}\text{embedded}\text{-}G_{max}\text{-}\text{core}$
. The
$\text{double}\text{-} \text{embedded} \text{-}G_{max}\text{-}\text{cort}$
is implemented by adopting an additional linear, lossless, and reciprocal (LLR) network that satisfies the
$G_{max}\text{-}\text{condition} (Y_{21}/Y_{12}=\text{-}G_{max})$
on to an
$N\text{-}\text{stage}\ \ \text{pseudo}\text{-}G_{max}\text{-}\text{cores}$
where each stage satisfies the stability factor
$k_{i}\!\!=\!\!1$
and phase delay of
$2\mathrm{m}\pi/N$
. Implemented in a 65nm CMOS, the three-stage 280.2 and 309.2 GHz amplifiers achieve power gains of 18.2 and 9.3 dB and gain-per-mW of 1.48 and 1.4 dB/mW, respectively.