A 10-bit 50-MS/s Asynchronous SAR ADC in 65nm CMOS

A 10-bit 50MS/s Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) in TSMC 65nm CMOS process with a 1.2-V supply voltage. The high three bits of Digital-to-Analog Converter (DAC) capacitor array are split, and the split-monotone switching control scheme is adopted. The remaining capacitors are all controlled by monotone switching scheme. The structure of split high capacitor can reduce the charge and discharge time of high capacitor, improve the sampling rate of circuit and reduce the power consumption of DAC. This DAC structure can reduce the offset of the comparator due to the variation of the common-mode input voltage. The asynchronous logic used in this paper produces a high frequency control signal matching the circuit conversion, without adding high frequency clock signal, which greatly reduces the design difficulty. Simulation results show that the SAR ADC achieves 52.09 SNDR and 8.36b ENOB at the input signal of 24.21875 MHz and the sampling rate of 50 MS/s, and consumes 2.79 mW of power.