Modeling and verification of iterated systems and protocols

The high complexity of modern hardware systems necessitates the use of formal methods for checking the satisfaction of desired properties and the absence of design flaws. Some powerful methods such as model checking and the to-automata approach have found wide acceptance, but suffer from the "state explosion" problem. To avoid this issue we recently proposed a new formal verification method based on series parallel posets. The technique is applicable to verifying the proper sequencing of events occurring in non-iterated, as well as globally-iterated/locally-non-iterated systems. In this paper we extend the series parallel poset verification to handle the much broader class of general iterated systems. This allows us to model and verify the behavior of systems involving feedback on multiple levels, as well as the behavior of communication, interconnect, and cache coherence protocols. The verification algorithms retain a low-order polynomial space- and time complexity.