Implementation, verification and synthesis of the Gigabit Ethernet 1000BASE-T physical coding sublayer

IEEE standard 802.3ab 1000BASE-T (Gigabit Ethernet) physical layer standard offers a cost-effective solution that upgrades the existing networks to 1000 Mbps data rates. It provides 1 Gbps Ethernet signal transmission over four pairs of category 5 unshielded twisted pair (UTP) cable using the 5-level coding scheme. The Physical Coding Sublayer (PCS) of this standard was simulated using Verilog HDL and synthesized using Synopsys. Two synthesis techniques, hierarchical optimization and hierarchical-flattening optimization, were chosen to compare the tradeoffs between them. The automation of the synthesis was accomplished with the synthesis script files.