Algorithmic Optimisation of Chip Dimensions and Layout Pattern in Press-Pack IGBT Devices

For press-pack IGBT devices manufactured using square chips in circular housings, it is necessary to optimise the dimensions of the chips in order to make the best use of the electrode area of the package. The objective of this optimisation process is to maximise the total active chip area within the device, so as to minimise on-state voltage and maximise the reverse bias safe operating area of the finished product. To maximise the total active chip area, it is critical to find an optimum balance between the area of the circular electrode filled with chips and the area of each chip taken up by invariant design features such as the gate pad and edge termination, which reduce the chip area available for conduction. These challenges imply opposite solutions: to maximise the usage of electrode area, smaller chips are preferred, but to maximise the active area fraction for the chip, larger chip outline dimensions are required. Manufacturing constraints must also be considered, for example, the preference to use a single chip outline to facilitate the manufacture of devices based on package outline of different diameters. The challenge can be approached in a number of ways including both graphical and mathematical methods, however, this paper demonstrates an algorithmic solution to this problem. The algorithmic approach will be used to demonstrate the effects of chip size, chip shape and different layout philosophies.