VLSI Architecture of Saturation Based Image Dehazing Algorithm and its FPGA Implementation

Image dehazing performs a crucial role in various real-time applications such as remote sensing, Advance Driver Assistance System (ADAS), surveillance systems etc. Therefore, a hardware implementation of an image dehazing system with high efficiency and low hardware cost is very much desirable. In this paper, we have proposed a nine-stage pipelined hardware architecture for haze removal which uses saturation information of the hazy image as the basis to derive local airlight (atmospheric light) and transmission of the individual pixels of the dehazed image. Since we have used pixel-based approach, our method does not require any edge detection unit as in the patch-based approach to decide the pixel in a patch is on the edge or not. The proposed method can operate at 94.7 MHz and require 970 logic elements (LEs) when implemented on the FPGA platform.