FPGA Acceleration of a Stochastic Local Search Portfolio Solver for Boolean Satisfiability

Stochastic Local Search (SLS) methods are known to perform well for certain classes of Boolean Satisfiability (SAT) problems for which deterministic methods are impractical. Portfolio methods use multiple solvers in parallel to achieve fast convergence. This paper discusses an SLS portfolio SAT solver implemented on a state-of-the-art FPGA-based hardware accelerator. The solver implementation uses multiple SLS algorithms running in parallel to handle SAT problems of varying degrees of difficulty. The solver also uses multi-threading and global accessing techniques to take advantage of the resources available in the Xilinx Alveo U280 accelerator card. We also introduce an Integrated Random Variable Selection (IRVS) technique to control the search space. This enables the use of multiple algorithms in our kernel architecture to better handle different types of problems. These features result in a capable hardware SLS solver that offers better speed and capacity than modern CPU based solvers.