A 50MHz Bandwidth TIA Based on Two Stage Pseudo-Differential OTA with Cascode Negative Resistance and R-C Compensation Technique

A 50MHz bandwidth(BW) transimpedance amplifier(TIA) is reported for 5GSub6GHz SAW-less wideband receivers. Traditional TIAs suffer from input impedance(Zin) peaking, which is detrimental to the linearity. This work aims to eliminate the peaking and achieve a Zin as low as possible. For this reason, an operational transconductance amplifier(OTA) with a very high unity-gain bandwidth(UGB) is designed. The gain is enhanced by cascode, and short-channel length MOSFETs are used to expand the BW. Due to the limited voltage headroom of the advanced process, a two-stage pseudo-differential structure without tail current source is adopted. A novel combination of negative resistance(NR) and cascode technology stabilizes the common-mode loop without sacrificing gain. Advanced R-C compensation technique is used to improve the phase margin(PM) of wideband OTA with no additional power consumption and UGB penalty. The post-layout simulation results show that the DC gain of the OTA is 41dB, the unity-gain loop bandwidth(UGLB) is 1GHz, and the PM is 47°. The derived TIA has an in-band(IB) IIP3 of 34.1dBm, an out-of-band(OOB) IIP3 of 44. 8dBm when IM3 is located at 39MHz. Zin is below $19\Omega$ at all frequencies. The whole chip only consumes 8. 5mW under 1. 2V supply.