Low Switching Loss Dual RESURF 40 V N-LDMOS with Grounded Field Plate for DC-DC Converters

This paper describes the optimization of the field plate formation for a µm CMOS compatible dual RESURF 40 V N-channel LDMOS transistor that we proposed to reduce the switching loss for buck type and boost type DCDC converters used in automotive applications. The field plate of the proposed device connects to the ground, which makes the Miller capacitance smaller significantly, causing much lower switching loss. We have optimized the length of the field plate $L_{F P}$ and the oxide thickness between the field plate and the drift region $T_{O X 1}$ to obtain the breakdown voltage between the drain and the source $B V_{D S}$ of more than 60 V with holding low switching loss by simulation. When the range of mass production variation for $L_{F P}$ is 200 nm and that for $T_{O X 1}$, 50 nm, the total switching loss during turn-on and turn-off $E_{T_{-} L o s s}$ is $7.90 \times 10^{-8}$ J/mm
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at the maximum, $7.49 \times 10^{-8}$ J/mm
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at the minimum. The $E_{T_{-} L o s s}$ of the proposed device in the range reduces to about 50 % that of the conventional LDMOS transistor, whose field plate connecting to the gate is only different from the proposed device. The proposed device also shows a switching loss of 0.077 W/mm
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at a high switching frequency of 1 MHz, and it has a conduction loss of 1.115 W/mm
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at a duty ratio of 0.5. Therefore, the proposed device has a much lower switching loss. Furthermore, the proposed device may enhance ESD endurance in the optimized range due to the breakdown generation near the drain terminal without filamentation in the drift region.