Ferroelectric-Semiconductor Tunnel Junction With Ultrathin Semiconductor Electrode Engineering

The relatively large total device dimension (
${L}_{\rm Tot}$
) of Ferroelectric-Semiconductor Tunnel Junctions (MFIS-FTJs) strictly obstructs their potential for hyper-scaling 3D integration. Towards such an issue, we propose an engineered MFIS-FTJ with the ultrathin semiconductor electrode (SE). The design rule for MFIS-FTJs with ultrathin SE is also investigated, considering voltage redistribution, SE thickness limitation, and quantum confinement effect. With careful design, our MFIS-FTJs with an 8.5 nm-thick SE achieve an ultrascaled
${L}_{\rm Tot}$
around 10 nm and acquire ~40 times enhancement in the tunneling electroresistance ratio over the bulk reference devices. This opens up a feasible pathway for
${L}_{\rm Tot}$
scaling in MFIS-FTJ and is instructive for practical application.