Bottom Dielectric Isolation to Suppress Sub-Fin Parasitic Channel of Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

In this paper, to suppress the parasitic channel of sub-fin in vertically stacked gate-all-around (GAA) Si nanosheet FETs (NSFETs), the bottom dielectric isolation (BDI) was designed and simulated using TCAD simulation. The results show that the sub-threshold characteristics of the n-type NSFETs are improved by the BDI approach, and the gate capacitance is reduced by 16.98% compared with that of the NSFETs with sub-fin. In addition, the BDI technology can increase the process and electrical stability of the NSFETs.