14 Bits Current DAC Testing with 16 Bits Instruments

In this paper the authors describe a pedestal-based method coupled with sub-ranging VI and current summing nodes for measuring source/sink current generators driven by 14 bits DACs. We will show how to implement it using 16 bits DACs/ ADCs VI sources, they can be used for testing current DACs linearity parameters like DNL/INL. The modern instruments have other techniques like oversampling and dithering can obliterate the discrete nature of the underlying ADCs & DACs, but in this paper, the authors will focus on elaborating “pedestal-based” method test concept. The pedestal source doesn't perform any measure and its effect is calibrated directly by the sub-ranging VI. It can be shared across several source/sink current DACs to avoid multiple pedestals. The sub-ranging VI source measures the DAC's current with a small range to guarantee accuracy. The equivalent achievable accuracy is -at least- 3 bits higher than the 14 bits DACs under test.