Developing of CMP Head-to-Head Compensation Function for Gate Height Uniformity Control

The performance and yield of advanced devices directly depend on the control of within wafer uniformity during each chemical mechanical polishing (CMP) step, as multiple CMP steps have been developed to define the structure to meet the criteria of High-k metal gate (HKMG) devices. As a consequence, to meet the increasingly stringent requirements, advanced process control (APC) has become a common process regulating approach in the semiconductor industry, and the needs of APC function for CMP is increasing greatly along with the technology nodes advancing to 28nm and below. So far, APC has been used for within wafer uniformity (WiW) control based on consumable lifetime, but it cannot cover consumable variation. In this paper, a novel and useful APC model is built to achieve head-to-head (HtH) compensation function to control within wafer uniformity, especially for wafer extreme edge (WEE), during each period maintain (PM) cycle of machine. This function is developed for gate height uniformity control of inter-layer dielectric level zero (ILD0) CMP.