Optimization of Metal Line Thickness & CD and Effect on RC Delay

In order to improve device performance, smaller resistance (R) and capacitance (C) in back-end-of-line (BEOL) metallization are pursued as two key technological boosters in minimizing time delay in lead-edge CMOS devices. R is inversely proportional to metal line cross sectional area, which is approximately the product of CD and thickness, while C is proportional to metal line thickness and reciprocal to metal line space (pitch - CD). Thus, a trade-off exists with respect to metal line CD and thickness to obtain desirable RC delay performance. Additionally, with continuous metal line scaling, R is further impacted by irregular trench shapes and electron surface scattering, which poses further challenges in CD and line thickness optimization. In this paper, the effects of metal line thickness and CD on RC is investigated through virtual fabrication method and electrical analysis of structures obtained. A systematic investigation is carried out to evaluate the impact of metal line thickness and CD calibrated on wafer structures.