Localized Pattern Loading Improvement of SOC Recess Process for Airgap Spacer

Airgap spacer is one of the promising transistor performance knobs for next-generation logic semiconductor applications. Existence of airgap spacer between metal gate and source/drain contact leads to a further reduction of parasitic capacitances. Nevertheless, a well-controlled air gap shape with low-k material surrounded, which is mainly defined by integration scheme and dummy spacer removal step, is not trivial and represents the main realization challenge in the field. Here, a novel airgap spacer scheme featuring with SOC recess step is introduced. However, SOC recess process is still a challenge for manufacturing, due to SOC thickness variation between dense and isolate regions. In this investigation, local uniformity improvement of SOC remaining thickness is achieved via combined advances in two-step plasma recess and DEDE method (deposition-etch-deposition-etch method). It provides new insights into SOC recess process involved in airgap spacer formation scheme and offers ideal guideline and framework for improvement of local uniformity in SOC recess process.