CMP Scratch Improve in Advanced Technology Nodes

In the advanced-tech node's shallow trench insulation (STI) chemical mechanical planarization (CMP) process development, by doing design of experiments (DOEs) and repeat runs, the scratch defect count was successfully reduced and kept at 5 count per wafer. In the beginning of development, the process, consumables and tool were used 28nm node's. The scratch defect count in begin was >200eas. The following development improved defect count to 100, 10 at different phases, and finally kept it at 5 count per wafer. The experiment data showed that the updated consumables, improved process parameters, condition type and optimized rinse steps all three factors had significant benefits to scratch defect reduction.