Process Window Integration Rule Check for Beol in Advanced Tech Node

As the technology node continuously shrinks in semiconductor manufacturing, the multi-patterning method is used extensively, especially for BEOL layers. In a process of LELE (litho-etch-litho-etch) with cut layers, the relationship between each sub-patterning layer becomes critical for the fidelity of the original design transition, as well as the patterning process window. This paper introduces a defect detection method based on resist model simulation. The method detects the exact location according to the OPC simulation result to find the potential defects. Compared with the traditional method of image comparison, the new method could improve the detection speed and accuracy greatly. Besides, traditional defect detection methods lack quantitative defect evaluation criteria, but the new method introduced in this article can provide a numerical basis for defect detection and the continuous optimization for defect evaluation algorithm. In addition, the actual wafer defect data, not only could be used to optimize OPC target and reduce defect generation, but also could provide wafer data support for searching potential weak points based on OPC simulation, and optimizing OPC weak points spec continuously, and further improving defect detection efficiency. This paper takes a cut-missing defect as an example, and designs splits of cut enclosure length on mask to find out the minimum safe enclosure of cut pattern when cut layers and metal lines overlaid, especially in consideration of BEOL production process window. The experiment of PWIRC (Process Window Integration Rule Check) is of great significance to the good transition and graphic function of the original design, as well as the improvement of mass production process and yield.