Influence of Parasitic Capacitance and Resistance on Performance of 6T-SRAM for Advanced CMOS Circuits Design

In this paper, the impacts of parasitic capacitance and resistance on the performance of 6T-SRAM are investigated comprehensively by a design-technology co-optimization (DTCO) method and TCAD simulation. It is found that the impact of parasitic capacitance on 6T-SRAM read and write operations is all adverse. However, the influence of parasitic resistance on 6T-SRAM is double-sided and can be used to improve the performance of 6T-SRAM. An optimization strategy of layout and route is proposed for SRAM with high speed, high noise stability or high read and write capabilities. These results provide a useful guidance for the 6T-SRAM layout design toward advanced node CMOS circuits.