A System-Level Post-Silicon Validation Methodology for High-Speed Serial Interfaces

High-Speed Serial IO interfaces supporting data rates of several tens and hundreds of giga bits per second are ubiquitous in today's server and client platforms for chip-to-chip and board-to-board communications. Careful system level validation of these interfaces is critical for high quality product releases and is challenging in the constraints of tight validation cycles. This paper presents a post-silicon validation methodology applicable to such interfaces that is proven to be efficient in detecting bugs, both at the silicon and system level, enabling high-quality product releases on time.