Design of a Programmable Low Power Linear Feedback Shift Register for BIST Applications

In this paper, a programmable low power linear feedback shift register for BIST applications has implemented in Xilinx Vivado Suite 2019. The design is parameterizable for 'n-bit’ polynomials and the seed value of user choice. Moreover, the design has a unique methodology of forcing low signal 0s in the dissimilar vector bits before the switching transition of registers and as well as incorporating the combination of two stage LFSRs (DT-LFSR) which could successfully reduce the number of output vector transition by ~70% with respect to the conventional LFSRs and hence significant reduction in dynamic power due to switching activity between adjacent vectors. The design has synthesized and simulated for 4,8-,16-,32- and 64-bit LFSR of different polynomials