TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC's

The efficient methodology to increase the yield and performance of 3D Stacked Integrated-Circuits (3D SICs) using TSV BIST Repair mechanism is addressed in this paper. This technique provides a promising solution to overcome power and interconnect congestion issues encountered during TSVs pre-bond and post-bond tests of 3D stacked ICs. The proposed TSV BIST Repair approach has the ability to identify short, open, pin-hole, void and break defects in TSV bonding. In response to these defects, the repair mechanism will provide redundancy analysis and repairable features to defective TSVs. Finally, the complete analysis of the proposed TSV BIST repair methodology shows significant improvement of 14.5% yield and test cost by potentially recovering all eminent defective chips.