Experimental setup for Hardware Encryption logic evaluation for e-learning

As a consequence of the globalization of the fabrication processes and semiconductor design, the integrated circuit (IC) is becoming increasingly vulnerable to malicious attacks. A hardware attack affects the existing design of the IC, with potential effects leading to the loss of information or its complete destruction. In this paper the hardware obfuscation process is presented. Logic encryption is the most secure hardware technique to prevent illegal overproduction of IC and Intellectual property (IP). An experimental setup for testing logically encrypted circuits to be used mainly for e-learning purposes is proposed. It allows analyzing different parameters of the encrypted circuit, as the error bits generated through wrong key bits with different locations of the encrypting gates. The setup is illustrated with XOR/NXOR encryption logic designs, described in VHDL and implemented at the gate level on FPGA. The setup will help student to understand and analyze the results of the application of the logic encryption techniques.