On the Performance of Thermoelectric Energy Generators by Stacked Thermocouples Design in CMOS Process

A semiconductor thermoelectric energy generator (TEG) with a stacked thermocouple design is developed to increase thermocouple density and achieve superior harvesting performance competitive to the BiTe-based TEGs. The stacked thermocouple design is by having the P-polysilicon layer above the N-polysilicon layer, such that the thermocouple has 1/2 footprint compared with the coplanar thermocouple design. For a TEG implemented by the standard complementary metal–oxide–semiconductor (CMOS) process [Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-
$\mu \text{m}$
two polysilicon layers and four metal layers (2P4M)], the 64-
$\mu \text{m}\,\,\times $
2-
$\mu \text{m}$
thermocouple of thickness 0.455
$\mu \text{m}$
(0.275-
$\mu \text{m}$
P-thermoleg above 0.180-
$\mu \text{m}$
N-thermoleg) can achieve 0.084-
$\mu \text{W}$
/cm2K2 power factor and 9.136-V/cm2K voltage factor in analysis and 0.075
$\mu \text{W}$
/cm2K2 and 7.004 V/cm2K in experiment. Both factors are about twice over those of the TEG with coplanar thermocouples, and they are significantly superior to all TEGs with polysilicon thermocouples. The TEG performance can be increased further by stacking more thermocouples and/or by adopting polysilicon layer(s) of higher Seebeck effect. For a TEG with one stacked thermocouple by the CMOS process [TSMC 0.18-
$\mu \text{m}$
one polysilicon layer and six metal layers (1P6M)], the polysilicon layer of higher thermoelectric conversion efficiency can achieve 0.476-
$\mu \text{W}$
/cm2K2 power factor and 60.811-V/cm2K voltage factor.