Performance Analysis of Multistage Cross-Coupled Differential-Drive Rectifiers using Simulations on 65nm CMOS Process

In this paper, the effect of varying transistor widths, rectifier stages, and threshold voltage on the performance of cross-coupled differential-drive rectifiers using a 65nm CMOS process are observed through simulations with a resistive load. Improving conversion efficiency has mostly been the focus for radio frequency (RF) rectifiers used in RF energy harvesting (RFEH) where the input power is expected to be small. Input impedance is also another concern since the matching network between the antenna and rectifier may introduce power loss due to reflections. However, it has been difficult to accurately model and predict the performance and characteristics of these rectifiers because of their non-linearity. Instead of relying on calculations, data from simulations is used to summarize the effects of various design decisions and come up with a suitable design given target specifications. Results show that the same output specifications can be achieved with less rectifier stages by using higher threshold transistors. This design achieves approximately the same conversion efficiency at the same input power level with a higher input resistance which helps increase the voltage gain for impedance matching networks for the rectifier.