A Fully Analytical Current Model for Gate–Source Overlap Tunneling FETs as the Ternary Devices

Gate–source overlap tunneling FETs (GSO-TFETs) as a novel ternary device are very promising in low-power neuromorphic circuits. In this article, an accurate potential model of the ternary GSO-TFETs is presented for the face-tunnel region considering the quasi-mobile charges (QMCs) based on the analysis of the face-tunnel mechanism. Then a potential-based analytical current model is developed for the first time to predict the face-tunnel process and line-tunnel current simultaneously with both the gate and the drain modulations. The modeling results are validated with TCAD simulations and good agreement within a wide biasing range is achieved, which indicates the great potential of this SPICE-friendly model for the tunneling-based ternary device in the commercial IC design fields.