Implementation of a 32-Bit RISC-V Processor with Cryptography Accelerators on FPGA and ASIC

This paper describes the use of a combination of hardware construction languages SpinalHDL and Verilog HDL to implement a 32-bit Linux-capable RISC-V processor with cryptography accelerators on an FPGA. LiteX and SpinalHDL are two intertwined frameworks in the design flow. The CPU core was created with SpinalHDL, while the integration of IP and CPU cores was performed with LiteX. Verilog source code was generated with the configured 32-bit RISC-V architecture after the design was completed on the high-level framework. This 32-bit RISC-V architecture was successfully built on a Nexys4DDR FPGA and ASIC using a 65nm CMOS process operating at 50MHz. It incorporated Verilog HDL-based hardware accelerators with customized assembly instructions for conventional cryptographic functions such as SHA-1, AES-128, and RSA-2048 cores. The functions of the accelerators were tested using a modified OpenSSL and LibreSSL library on Linux.