Reduction of Common-Mode Voltage Using Zero Voltage Vectors in Dual Star Asymmetrical Induction Motor

This article proposes modified carrier-based pulse width modulation techniques and space vector modulation techniques which generate the least Common-mode Voltage in dual star asymmetrical induction motor. Initially, standard sine PWM and standard zero sequence PWM techniques are studied using the SVM approach, which gives the maximum CMV (
+
0.5·V
_dc
). In the plane of dual star SVM, two pairs of zero voltage vector are characterized as maximum CMV and zero CMV, respectively. By utilizing one pair of ZVV, which offers zero CMV, four new switching patterns are proposed that reduce CMV by 66.8% compared to standard PWM techniques. These techniques provide the least CMV (
+
0.166·V
_dc
) and are easily implemented in the C-programming of controllers. One of the proposed technique (DCMV-A2) provides the least stator current distortion over the entire modulation range and switching losses when the machine is operated at 0.92
<
p.f.
<
1. All PWM techniques are validated through an analytical method, MATLAB Simulink model, and experimental setup of DSAIM.